1. Field of the Invention
The present invention relates generally to flip chip technology. More particularly, the present invention relates to a flip chip package utilizing trace bump trace (TBT) interconnection.
2. Description of the Prior Art
In order to ensure miniaturization and multi-functionality of electronic products or communication devices, semiconductor packages are required to be of small in size, multi-pin connection, high speed, and high functionality. Increased Input-Output (I/O) pin count combined with increased demands for high performance ICs has led to the development of flip chip packages.
Flip-chip technology uses bumps on chip to interconnect the package media such as package substrate. The flip-chip is bonded face down to the package substrate through the shortest path. These technologies can be applied not only to single-chip packaging, but also to higher or integrated levels of packaging in which the packages are larger and to more sophisticated substrates that accommodate several chips to form larger functional units. The flip-chip technique, using an area array, has the advantage of achieving the higher density of interconnection to the device and a very low inductance interconnection to the package.
FIG. 1 shows a portion of a conventional flip chip package in a diagrammatic sectional view. As shown in FIG. 1, the conventional flip chip package 1 is made by using a “bump-on-capture pad” (BOC) interconnect scheme. At least two adjacent capture pads 21a and 21b and a metal trace 22 are disposed on a die attach surface of the package substrate 2. A solder mask 26 covers the die attach surface of the package substrate 2. The solder mask 26 has solder mask defined (SMD) openings corresponding to the capture pads 21a and 21b for confining the flow of solder during the interconnection process.
Interconnection solder bumps 31a and 31b disposed on the active side of the die 3 are joined to the exposed capture pads 21a and 21b respectively. After performing the reflow of the interconnection solder bumps 31a and 31b, an underfill material 4 is typically introduced into the gap with stand-off height h between the substrate 2 and the die 3 to mechanically stabilizing the interconnects.
One drawback of the above-described prior art is that there is considerable loss of routing space on the top layer of package substrate 2. This is because the width or diameter of the capture pad is typically about the same as the ball (or bump) diameter, and can be as much as two to four times wider than the trace (or lead) width. Another drawback of the above-described prior art is that the small stand-off height between the die and the package substrate limits the process window, reliability and throughput when performing underfill process in the flip chip assembly flow.